CPRE381 · Computer Architecture

Pipelined Processors —
hardware design.

Designed and simulated pipelined CPU architectures in VHDL, exploring ISA design, hazard mitigation, forwarding logic, and memory hierarchy performance.

overview

What I
built.

In CPRE381 I delved into computer organisation and performance evaluation by designing and simulating pipelined processor architectures in VHDL. The centrepiece project was a 5-stage scalar pipeline CPU featuring an ALU, control unit, hazard detection, and forwarding logic to optimise instruction throughput.

To validate design correctness I authored comprehensive VHDL test benches and used ModelSim to generate waveform outputs, analysing timing diagrams and resolving data/control hazards. I also implemented assembly-level test programs to exercise instruction set features, measured CPI, and experimented with memory hierarchy setups to evaluate cache impacts.

This immersive coursework strengthened my understanding of ISA design, pipeline control, performance trade-offs, and hardware description languages — foundations critical for low-level systems and embedded development.

highlights

Key
contributions.

5-Stage Pipeline CPU
Engineered a complete scalar pipeline with fetch, decode, execute, memory, and write-back stages in VHDL, including hazard detection and data forwarding.
VHDL Test Benches
Wrote comprehensive test benches to validate each pipeline stage, using ModelSim waveform analysis to identify and resolve timing issues.
ISA & Assembly Testing
Implemented assembly-level programs to exercise instruction set features, measure CPI, and verify correct execution through simulation.
Cache & Memory Hierarchy
Experimented with memory hierarchy configurations to evaluate cache impacts on processor performance and throughput.

technology

Stack &
tools.

Hardware design and simulation workflow centred on VHDL with ModelSim for waveform verification and MIPS assembly for functional testing.
VHDL ModelSim MIPS Assembly Pipeline Design Hazard Detection Cache Design
View Code on GitHub →