In CPRE381, I delved into computer organization and performance evaluation by designing and simulating pipelined processor architectures in VHDL. Projects included an 5-stage scalar pipeline CPU featuring an ALU, control unit, hazard detection, and forwarding logic to optimize instruction throughput.
To validate design correctness, I authored comprehensive VHDL test benches and used ModelSim to generate waveform outputs, analyzing timing diagrams and resolving data/control hazards. I also implemented assembly-level test programs to exercise instruction set features, measured CPI, and experimented with memory hierarchy setups to evaluate cache impacts.
This immersive coursework strengthened my understanding of ISA design, pipeline control, performance trade-offs, and hardware description languages—foundations critical for low-level systems and embedded development.